Vertical TFT with tunnel barrier

ABSTRACT

A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.

BACKGROUND

The present disclosure relates to technology for non-volatile storage.

Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in personal navigation devices, cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.

Some EEPROMs or flash memory devices have a configuration referred to as a NAND configuration in which memory cells are grouped as NAND strings with each NAND string associated with a bit line. One type of NAND memory array is a two-dimensional array. Another type of NAND memory array is a three-dimensional array. One 3D NAND stacked memory device is sometimes referred to as a Bit Cost Scalable (BiCS) architecture.

In a 3D NAND BiCS architecture, a 3D NAND stacked memory device can be formed from an array of alternating conductor and insulator layers. A memory hole is drilled in the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory hole with appropriate materials. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a pipe connection. Control gates of the memory cells are provided by the conductor layers.

Another example of non-volatile memory uses variable resistance memory elements that may be set to either low or high resistance states. Upon application of sufficient voltage, current, or other stimulus, the variable resistance memory element switches to a stable low-resistance state, which is sometimes referred to as SETTING the device. This resistivity-switching is reversible such that subsequent application of an appropriate voltage, current, or other stimulus can serve to return the reversible resistivity-switching material to a stable high-resistance state, which is sometimes referred to as RESETTING the device. This conversion can be repeated many times.

The variable resistance memory elements may be in a high resistance state when first manufactured. This may be referred to as the “virgin state.” In the virgin state, the resistance could be even higher than for the RESET state. The term “FORMING” is sometimes used to describe putting the variable resistance memory elements into a lower resistance state for the first time. For some memory elements, the FORMING operation requires a higher voltage than the SET and/or RESET operations.

3D memory arrays having variable resistance memory elements have been proposed.

In one possible architecture, word lines extend horizontally and bit lines extend vertically. There a multiple levels of the word lines, hence multiple levels of memory elements. Each memory element is located between one of the vertical bit lines and one of the horizontal word lines. During operation, some of the memory cells are selected for the SET, RESET, or FORM operation, while others are unselected.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of one embodiment of a thin film transistor (TFT) having a tunnel barrier.

FIG. 2A is an equivalent circuit of a portion of an example three-dimensional array of variable resistance memory elements, wherein the array has vertical bit lines.

FIG. 2B is a schematic block diagram of a re-programmable non-volatile memory system which utilizes the memory array of FIG. 2A, and which indicates connection of the memory system with a host system.

FIG. 3 provides plan views of the two planes and substrate of the three-dimensional array of FIG. 2A, with some structure added.

FIG. 4 is an expanded view of a portion of one of the planes of FIG. 3, annotated to show effects of programming data therein.

FIG. 5 is an expanded view of a portion of one of the planes of FIG. 3, annotated to show effects of reading data therefrom.

FIG. 6 is an isometric view of a portion of the three-dimensional array shown in FIG. 2A according to a first specific example of an implementation thereof.

FIG. 7 is an equivalent circuit of a portion of an example three-dimensional array of variable resistance memory elements, wherein the array has vertical bit lines and a pillar select layer, both of which are above (and not in) the substrate.

FIG. 8A is a schematic that depicts a vertical bit line, a vertically oriented select device and a global bit line.

FIG. 8B is a plan view that depicts a vertical bit line, a vertically oriented select device and a global bit line.

FIG. 9 is a schematic of a portion of the memory system, depicting vertical bit lines above the substrate, vertically oriented select devices above the substrate and row select line drivers in the substrate.

FIGS. 10A-10D depict various embodiments of vertical TFTs with tunnel barriers.

FIG. 11A is a cross-sectional view of a memory structure using one embodiment of a vertically oriented TFT select device and the memory structure of FIG. 6.

FIG. 11B is a cross-sectional view of another embodiment of a memory structure and the memory structure of FIG. 6.

FIG. 12 is a schematic of a portion of the memory system, depicting vertical bit lines and vertically oriented select devices above the substrate.

FIG. 13 is a schematic of a portion of the memory system, depicting vertical bit lines, vertically oriented select devices above the substrate and row select line drivers in the substrate.

FIG. 14 is a flow chart describing one embodiment of a process for fabricating a 3D memory array having a vertical TFT selector with a tunnel barrier.

FIGS. 15A-15E depict formation of the structure during the process of FIG. 14.

FIG. 16 is a circuit representation of a NAND string.

FIG. 17 is a perspective view of a 3D stacked non-volatile memory device.

FIG. 18 depicts an embodiment of block BLK0 of FIG. 17.

FIG. 19 depicts a cross-sectional view of a block of the 3D non-volatile memory device of FIG. 18 having straight strings.

FIG. 20A depicts a close-up view of the region 2069 of FIG. 19.

FIG. 20B depicts a cross-sectional view of the column C0 of FIG. 20A.

FIG. 21 depicts a close-up view of the region 2089 of FIG. 19.

DETAILED DESCRIPTION

Disclosed herein is a vertical thin film transistor (TFT) having a tunnel barrier and methods for fabricating the same. The vertical TFT with tunnel barrier serves as a selection device, in one embodiment. In one embodiment, the vertical TFT with tunnel barrier is used as a selection device in a 3D memory device. For example, the vertical TFT could be used to select a vertical bit line or a vertical NAND string. In one embodiment, the tunnel barrier comprises an insulator between a source/drain region and a channel region. The vertical TFT has a high breakdown voltage. The vertical TFT has a high on current (I_(ON)). The vertical TFT has a low leakage current (I_(OFF)). Properties such as high I_(ON) allow the height of the vertical TFT to be reduced, while still providing sufficient I_(ON).

FIG. 1 is a diagram of one embodiment of a vertical TFT having a tunnel barrier. The vertical TFT 504 has first source/drain region 501 a, second source/drain region 501 b, channel region 502, tunnel barrier 509, gate(s) 507, and gate dielectric(s) 505. The tunnel barrier 509 may increase the breakdown voltage of the transistor. The tunnel barrier 509 may lower the leakage current (e.g., I_(OFF)) of the transistor. The tunnel barrier 509 acts as a tunneling oxide during operation, in one embodiment. Electrons can tunnel through the tunnel barrier 509 during operation, in one embodiment.

The tunnel barrier 509 is formed from an electrical insulator, in one embodiment. The tunnel barrier 509 is formed from a dielectric material, in one embodiment. Examples of the material for the tunnel barrier 509 include, but are not limited to, silicon oxide and hafnium oxide. In one embodiment, the tunnel barrier 509 is a layer of silicon oxide that is less than about 3.5 nm (3.5×10⁻⁹ meters) thick. However, the tunnel barrier 509 could be thicker than 3.5 nm whether or not formed from silicon oxide.

The first (or lower) source/drain 501 a is in electrical contact with a lower conductor 514. The second (or upper) source/drain 501 b is in electrical contact with an upper conductor 516. The vertical thin film transistor (TFT) 504 may be used as a switch to electrically connect/disconnect the lower and upper conductors 514, 516 to/from each other. This may allow the vertical TFT 504 to be used as a selection device.

The first source/drain region 501 a, the second source/drain region 501 b, and the channel region 502 are formed from a semiconductor, in one embodiment. As one example, they are formed from silicon, such a polysilicon. The first source/drain region 501 a and the second source/drain region 501 b have the same type of conductivity, in one embodiment. For example, they may each be P+ or may each be N+. The channel region 502 has a different type of conductivity than the source/drains 501, in one embodiment. In one embodiment, the regions 501 a, 502, 501 b are N+/P−/N+, respectively. In one embodiment, the regions 501 a, 502, 501 b are P+/N−/P+, respectively. The channel region 502 may be lightly doped or it may be intrinsic. The channel region 502 could also be referred to as a body. The channel region 502 acts as the channel of the TFT 504 during operation.

An example of the doping concentration is 7×10²⁰/cm³ for the source/drain regions 501 and 1×10¹⁷/cm³ for the channel region 502. Using a lower doping concentration in the channel region 502 can increase the on current (I_(ON)). It is possible that lowering the doping concentration in the channel region 502 could also increase I_(OFF). However, as noted already, the tunnel barrier 509 can decrease I_(OFF). These parameters (e.g., doping concentration in the channel region, tunnel barrier thickness) may be adjusted to achieve a balance between high I_(ON) and low I_(OFF). Additionally, the doping concentration in the source/drain regions 501 can be reduced to increase the breakdown voltage, as well as to increase I_(OFF).

In one embodiment, the vertical TFT 504 is used as a selection device in a memory array. As one example, the vertical TFT 504 is used to select vertical bit lines in a 3D memory array. As one example, the vertical TFT 504 is used to select vertical NAND strings in a 3D memory array.

An embodiment in which the vertical TFT 504 is used in a 3D memory array having vertical bit lines will now be discussed. Memory elements in a 3D memory array may be controlled by applying the proper voltages to their vertical bit lines and word lines. By applying either a select voltage or an unselect voltage to the vertical bit lines, while applying either a select voltage or an unselect voltage to the horizontal word lines, memory cells are selected/unselected for the operation (e.g., SET, RESET, and FORM). The vertically oriented TFT provides the proper voltage to the vertical bit line, in one embodiment.

It is important that unselected memory elements remain unselected. Selection of the vertically oriented bit lines themselves is achieved by a vertical TFT, in one embodiment. Typically, some of the vertical TFTs are turned on to select memory elements, while other vertical TFTs are kept off to keep other memory elements unselected. In this manner the vertical TFTs provide suitable voltages to the vertically oriented bit lines. Word lines are driven with suitable voltages, as well.

One potential problem with the transistor that selects the vertically oriented bit lines is that the transistor may not have a sufficiently high breakdown voltage. If a transistor selection device that is supposed to be off breaks down, then the transistor could apply an unintended voltage to the vertically oriented bit line. Thus, having a high breakdown voltage is an important characteristic. This can be especially important when performing a FORMING operation, although a high breakdown voltage may also benefit SET and RESET operations.

Even if the transistor that is supposed to be off is not in a breakdown regime, but has high leakage current, it can pass an unintended voltage to the vertically oriented bit line. The higher the leakage the faster the unintended voltage can pass to the bit line (the faster the vertical bit line can be charged up).

The transistor leakage can have several components, such as source-drain leakage and leakage related to carrier generation due to high electric field, such as band-to-band generation, trap-assisted generation, etc. All components of the leakage will represent transistor current in the off state—I_(OFF). For instance, when the gate to drain potential difference is high enough, band-to-band generation may occur, resulting in increased leakage. This is sometimes is referred to as GIDL—gate induced drain leakage.

High gate to drain potential difference also results in high electric field component in the direction perpendicular to the gate dielectric (perpendicular to the direction of channel) contributing to overall electric field increase. The total electric field at the gate/drain edge is then determined by the lateral, or along the channel, field component (dependent on source to drain bias) and the perpendicular to the channel component of the field. When total field is high enough (i.e., voltages high enough), this can trigger impact ionization-generation and breakdown.

If the applied voltage (e.g., drain to source potential difference) is approaching breakdown voltage, the leakage rapidly increases. Therefore if transistor breakdown voltage is increased, the leakage is lower for the same applied voltage(s). Therefore it is important to be able to increase the voltage at which breakdown occurs.

Also it is important to reduce GIDL, which is dependent on gate to drain potential difference.

Sometimes, I_(OFF) current can be reduced by making a transistor bigger, e.g., increasing transistor channel length. However, this may result in lower drive current (I_(ON)). For vertical bit line applications it is important for TFT to deliver high enough I_(ON) because the ReRAM memory cell often requires high enough current to switch from SET to RESET or/and vice versa. High I_(ON) may also be required for FORMING operation.

Another problem of bigger channel length is the transistor may become bigger. By bigger in the context of a vertically oriented selection device, this means that the TFT is longer in the vertical direction. In other words, the aspect ratio (height over body thickness ratio) may increase, which could make it more difficult to fabricate the TFT.

Therefore it is important to be able to optimize transistor parameters for the best combination or trade-offs for I_(ON), I_(OFF)/leakage and breakdown voltage in order to allow efficient operation of the selector device. Also, the smaller the channel length (in this context the vertical size of the transistor), the better it is from process point of view (lower aspect ratio).

In one embodiment, the vertical TFT having a tunnel barrier is used as a bit line selection device in a three-dimensional array of memory elements wherein bit lines of the array are oriented vertically. That is, instead of merely stacking a plurality of two-dimensional arrays on a common semiconductor substrate, where each two-dimensional array has its own bit lines, multiple two-dimensional arrays are stacked on top of each other in separate planes but then share common bit lines that extend up through the planes.

The memory elements used in the three-dimensional array are variable resistive memory elements, in one embodiment. That is, the resistance (and thus inversely the conductance) of the individual memory elements is typically changed as a result of a voltage placed across the orthogonally intersecting conductors to which the memory element is connected. Depending on the type of variable resistive element, the state may change in response to a voltage across it, a level of current though it, an amount of electric field across it, a level of heat applied to it, and the like. With some variable resistive element material, it is the amount of time that the voltage, current, electric field, heat and/or the like is applied to the element that determines when its conductive state changes and the direction in which the change takes place. In between such state changing operations, the resistance of the memory element remains unchanged, so is non-volatile. The three-dimensional array architecture summarized above may be implemented with a memory element material selected from a wide variety of such materials having different properties and operating characteristics.

The resistance of the memory element, and thus its detectable storage state, can be repetitively set from an initial level to another level and then re-set back to the initial level. For some materials, the amount or duration of the voltage, current, electric field, heat and the like applied to change its state in one direction is different (asymmetrical) with that applied to change in another direction. With two detectable states, each memory element stores one-bit of data. With the use of some materials, more than one bit of data may be stored in each memory element by designating more than two stable levels of resistance as detectable states of the memory element. The three-dimensional array architecture herein is quite versatile in the way it may be operated.

This three-dimensional architecture also allows limiting the extent and number of unaddressed (non-selected) resistive memory elements across which an undesired level of voltage is applied during reading and programming operations conducted on other addressed (selected) memory elements. The risk of disturbing the states of unaddressed memory elements and the levels of leakage current passing through unaddressed elements may be significantly reduced from those experienced in other arrays using the same memory element material. Leakage currents are undesirable because they can alter the apparent currents being read from addressed memory elements, thereby making it difficult to accurately read the states of addressed (selected) memory elements. Leakage currents are also undesirable because they add to the overall power draw by an array and therefore undesirably causes the power supply to have to be made larger than is desirable. Because of the relatively small extent of unaddressed memory elements that have voltages applied during programming and reading of addressed memory elements, the array with the three-dimensional architecture herein may be made to include a much larger number of addressed memory elements without introducing errors in reading and exceeding reasonable power supply capabilities. A vertical TFT having a tunnel barrier, in accordance with one embodiment, that selects vertical bit lines has a low leakage current.

In addition, the three-dimensional architecture herein allows variable resistance memory elements to be connected at orthogonal crossings of bit and word line conductors without the need for diodes or other non-linear elements being connected in series with the variable resistive elements. In some 3D arrays of variable resistance memory elements, a diode is connected in series with each memory element in order to reduce the leakage current though the element when it is unselected but nevertheless has a voltage difference placed across it, such as can occur when the unselected memory element is connected to a bit or word line carrying voltages to selected memory elements connected to those same lines. The absence of the need for diodes significantly reduces the complexity of the array and thus the number of processing steps required to manufacture it. The term connected refers to direct and indirect connections.

Indeed, the manufacture of the three-dimensional array of memory elements herein is much simpler than other three-dimensional arrays using the same type of memory elements. In particular, a fewer number of masks is required to form the elements of each plane of the array. The total number of processing steps needed to form integrated circuits with the three-dimensional array are thus reduced, as is the cost of the resulting integrated circuit.

Referring initially to FIG. 2A, an architecture of one embodiment of a three-dimensional memory 10 is schematically and generally illustrated in the form of an equivalent circuit of a portion of such a memory. A standard three-dimensional rectangular coordinate system 11 is used for reference, the directions of each of vectors x, y and z being orthogonal with the other two. In another embodiment direction x and x are substantially 60 degrees from each other.

A circuit for selectively connecting internal memory elements with external data circuits is preferably formed using select devices Q_(xy), where x gives a relative position of the device in the x-direction and y its relative position in the y-direction. The individual select devices Q_(xy) are vertical TFTs having a tunnel barrier, in accordance with embodiments. Global bit lines (GBL_(x)) are elongated in the y-direction and have relative positions in the x-direction that are indicated by the subscript. The global bit lines (GBL_(x)) are individually connectable with the source or drain of the vertical TFT select devices Q_(xy) having the same position in the x-direction, although during reading and also typically programming only one select device connected with a specific global bit line is turned on at time. The other of the source or drain of the individual select devices Q_(xy) is connected with one of the local bit lines (LBL_(xy)). The local bit lines are elongated vertically, in the z-direction, and form a regular two-dimensional array in the x (row) and y (column) directions.

In order to connect one set (in this example, designated as one row) of local bit lines with corresponding global bit lines, row select lines SG_(y) are elongated in the x-direction and connect with control terminals (gates) of a single row of vertical TFT select devices Q_(xy) having a common position in the y-direction. The vertical TFT select devices Q_(xy) therefore connect one row of local bit lines (LBL_(xy)) across the x-direction (having the same position in the y-direction) at a time to corresponding ones of the global bit-lines (GBL_(x)), depending upon which of the row select lines SG_(y) receives a voltage that turns on the vertical TFT select devices to which it is connected. The remaining row select lines receive voltages that keep their connected vertical TFT select devices Q_(xy) off. It may be noted that since only one vertical TFT select device (Q_(xy)) is used with each of the local bit lines (LBL_(xy)), the pitch of the array across the semiconductor substrate in both x and y-directions may be made very small, and thus the density of the memory storage elements large.

The vertical TFT select devices Q_(xy) have tunnel barriers. The tunnel barrier improves performance characteristics, such as breakdown voltage and Gate Induced Drain Leakage (GIDL). This helps to keep the vertical TFT select device off, when it should be off. It also helps keep leakage current low.

Memory elements M_(zxy) are formed in a plurality of planes positioned at different distances in the z-direction above a substrate (which may be below the pillar select layer). Two planes 1 and 2 are illustrated in FIG. 2A but there will typically be more, such as 4, 6, 8, 16, 32, or even more. In each plane at distance z, word lines WL_(zy) are elongated in the x-direction and spaced apart in the y-direction between the local bit-lines (LBL_(xy)). The word lines WL_(zy) of each plane individually cross adjacent two of the local bit-lines LBL_(xy) on either side of the word lines. The individual memory storage elements M_(zxy) are connected between one local bit line LBL_(xy) and one word line WL_(zy) adjacent these individual crossings. An individual memory element M_(zxy) is therefore addressable by placing proper voltages on the local bit line LBL_(xy) and word line WL_(zy) between which the memory element is connected. The voltages are chosen to provide the electrical stimulus necessary to cause the state of the memory element to change from an existing state to the desired new state. After the device is first fabricated, voltages may be selected to provide the electrical stimulus necessary to “form” the memory element, which refers to lowering its resistance from a virgin state. The levels, duration and other characteristics of these voltages depend upon the material that is used for the memory elements.

Each “plane” of the three-dimensional memory structure is typically formed of at least two layers, one in which the conductive word lines WL_(zy) are positioned and another of a dielectric material that electrically isolates the planes from each other. Additional layers may also be present in each plane, depending for example on the structure of the memory elements M_(zxy). The planes are stacked on top of each other above a semiconductor substrate with the local bit lines LBL_(xy) being connected with storage elements M_(zxy) of each plane through which the local bit lines extend.

The memory arrays described herein, including memory 10, may be monolithic three dimensional memory arrays. A monolithic three dimensional memory array is one in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other. The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.

FIG. 2B is a block diagram of an illustrative memory system that can use the three-dimensional memory 10 of FIG. 2A. Data input-output circuits 21 are connected to provide (during programming) and receive (during reading) analog electrical quantities in parallel over the global bit-lines GBL_(x) of FIG. 2A that are representative of data stored in addressed memory elements M_(zxy). Data input-output circuits 21 typically contain sense amplifiers for converting these electrical quantities into digital data values during reading, which digital values are then conveyed over lines 23 to a memory system controller 25. Conversely, data to be programmed into the array 10 are sent by the controller 25 to the input-output circuits 21, which then programs that data into addressed memory element by placing proper voltages on the global bit lines GBL_(x). For binary operation, one voltage level is typically placed on a global bit line to represent a binary “1” and another voltage level to represent a binary “0”. The memory elements are addressed for reading or programming by voltages placed on the word lines WL_(zy) and row select lines SG_(y) by respective word line select circuits 27 and local bit line circuits 29. In the specific three-dimensional array of FIG. 2A, the memory elements lying between a selected word line and any of the local bit lines LBL_(xy) connected at one instance through the select devices Q_(xy) to the global bit lines GBL_(x) may be addressed for programming or reading by appropriate voltages being applied through the select circuits 27 and 29.

Controller 25 typically receives data from and sends data to a host system 31. Controller 25 usually contains an amount of random-access-memory (RAM) 34 for temporarily storing such data and operating information. Commands, status signals and addresses of data being read or programmed are also exchanged between the controller 25 and host 31. The memory system operates with a wide variety of host systems. They include personal computers (PCs), laptop and other portable computers, cellular telephones, personal digital assistants (PDAs), digital still cameras, digital movie cameras and portable audio players. The host typically includes a built-in receptacle 33 for one or more types of memory cards or flash drives that accepts a mating memory system plug 35 of the memory system but some hosts require the use of adapters into which a memory card is plugged, and others require the use of cables therebetween. Alternatively, the memory system may be built into the host system as an integral part thereof.

Controller 25 conveys to decoder/driver circuits 37 commands received from the host 31. Similarly, status signals generated by the memory system are communicated to the controller 25 from decoder/driver circuits 37. The circuits 37 can be simple logic circuits in the case where the controller controls nearly all of the memory operations, or can include a state machine to control at least some of the repetitive memory operations necessary to carry out given commands. Control signals resulting from decoding commands are applied from the circuits 37 to the word line select circuits 27, local bit line select circuits 29 and data input-output circuits 21. Also connected to the circuits 27 and 29 are address lines 39 from the controller that carry physical addresses of memory elements to be accessed within the array 10 in order to carry out a command from the host. The physical addresses correspond to logical addresses received from the host system 31, the conversion being made by the controller 25 and/or the decoder/driver 37. As a result, the local bit line select circuits 29 partially address the designated storage elements within the array 10 by placing proper voltages on the control elements of the select devices Q_(xy) to connect selected local bit lines (LBL_(xy)) with the global bit lines (GBL_(x)). The addressing is completed by the circuits 27 applying proper voltages to the word lines WL_(zy) of the array.

Although each of the memory elements M_(zxy) in the array of FIG. 2A may be individually addressed for changing its state according to incoming data or for reading its existing storage state, it may be preferable to program and read the array in units of multiple memory elements in parallel. In the three-dimensional array of FIG. 2A, one row of memory elements on one plane may be programmed and read in parallel. The number of memory elements operated in parallel depends on the number of memory elements connected to the selected word line. In some arrays, the word lines may be segmented (not shown in FIG. 2A) so that only a portion of the total number of memory elements connected along their length may be addressed for parallel operation, namely the memory elements connected to a selected one of the segments. In some arrays the number of memory elements programmed in one operation may be less than the total number of memory elements connected to the selected word line to minimize IR drops, to minimize power, or for other reasons.

Previously programmed memory elements whose data have become obsolete may be addressed and re-programmed from the states in which they were previously programmed. The states of the memory elements being re-programmed in parallel will therefore most often have different starting states among them. This is acceptable for many memory element materials but it is may be preferred to re-set a group of memory elements to a common state before they are re-programmed. For this purpose, the memory elements may be grouped into blocks, where the memory elements of each block are simultaneously reset to a common state, preferably one of the programmed states, in preparation for subsequently programming them. If the memory element material being used is characterized by changing from a first to a second state in significantly less time than it takes to be changed from the second state back to the first state, then the reset operation is preferably chosen to cause the transition taking the longer time to be made. The programming is then done faster than resetting. The longer reset time is usually not a problem since resetting blocks of memory elements containing nothing but obsolete data is typically accomplished in a high percentage of the cases in the background, therefore not adversely impacting the programming performance of the memory system.

With the use of block re-setting of memory elements, a three-dimensional array of variable resistive memory elements may be operated in a manner similar to flash memory arrays. Resetting a block of memory elements to a common state corresponds to erasing a block of flash memory elements to an erased state. The individual blocks of memory elements herein may be further divided into a plurality of pages of storage elements, wherein the memory elements of a page are programmed and read together. This is like the use of pages in flash memories. The memory elements of an individual page are programmed and read together. Of course, when programming, those memory elements that are to store data that are represented by the reset state are not changed from the reset state. Those of the memory elements of a page that need to be changed to another state in order to represent the data being stored in them have their states changed by the programming operation.

An example of use of such blocks and pages is illustrated in FIG. 3, which provides plan schematic views of planes 1 and 2 of the array of FIG. 2A. The different word lines WL_(zy) that extend across each of the planes and the local bit lines LBL_(xy) that extend through the planes are shown in two-dimensions. Individual blocks are made up of memory elements connected to both sides of one word line, or one segment of a word line if the word lines are segmented, in a single one of the planes. There are therefore a very large number of such blocks in each plane of the array. In the block illustrated in FIG. 3, each of the memory elements M₁₁₄, M₁₂₄, M₁₃₄, M₁₁₅, M₁₂₅ and M₁₃₅ connected to both sides of one word line WL₁₂ form the block. Of course, there will be many more memory elements connected along the length of a word line but only a few of them are illustrated, for simplicity. The memory elements of each block are connected between the single word line and different ones of the local bit lines, namely, for the block illustrated in FIG. 3, between the word line WL₁₂ and respective local bit lines LBL₁₂, LBL₂₂, LBL₃₂, LBL₁₃, LBL₂₃ and LBL₃₃.

A page is also illustrated in FIG. 3. In the specific embodiment being described, there are two pages per block. One page is formed by the memory elements along one side of the word line of the block and the other page by the memory elements along the opposite side of the word line. The example page marked in FIG. 3 is formed by memory elements M₁₁₄, M₁₂₄ and M₁₃₄. Of course, a page will typically have a very large number of memory elements in order to be able to program and read a large amount of data at one time. Only a few of the storage elements of the page of FIG. 3 are included, for simplicity in explanation.

Example resetting, programming (e.g., setting) and reading operations of the memory array of FIG. 2A, when operated as array 10 in the memory system of FIG. 2B, will now be described. For these examples, each of the memory elements M_(zxy) is taken to include a non-volatile memory material that can be switched between two stable states of different resistance levels by impressing voltages (or currents) of different polarity across the memory element, or voltages of the same polarity but different magnitudes and/or duration. For example, one class of material may be placed into a high resistance state by passing current in one direction through the element, and into a low resistance state by passing current in the other direction through the element. Or, in the case of switching using the same voltage polarity, one element may need a higher voltage and a shorter time to switch to a high resistance state and a lower voltage and a longer time to switch to a lower resistance state. These are the two memory states of the individual memory elements that indicate storage of one bit of data, which is either a “0” or a “1,” depending upon the memory element state.

To reset (e.g., erase) a block of memory elements, the memory elements in that block are placed into their high resistance state. This state will be designated as the logical data state “1,” following the convention used in current flash memory arrays but it could alternatively be designated to be a “0.” As shown by the example in FIG. 3, a block includes all the memory elements that are electrically connected to one word line WL or segment thereof. A block is the smallest unit of memory elements in the array that are reset together. It can include thousands of memory elements. If a row of memory elements on one side of a word line includes 1000 of them, for example, a block will have 2000 memory elements from the two rows on either side of the word line.

The following steps may be taken to reset all the memory elements of a block, using the block illustrated in FIG. 3 as an example:

-   -   1. Set all of the global bit lines (GBL₁, GBL₂ and GBL₃ in the         array of FIGS. 2A and 3) to zero volts, by the circuits 21 of         FIG. 2B.     -   2. Set at least the two row select lines on either side of the         one word line of the block to H′ volts, so that the local bit         lines on each side of the word line in the y-direction are         connected to their respective global bit lines through their         select devices and therefore brought to zero volts. The voltage         H′ is made high enough to turn on the vertical TFT select         devices Q_(xy), for example, something in a range of 1-6 volts,         typically 3 volts. The block shown in FIG. 3 includes the word         line WL₁₂, so the row select lines SG₂ and SG₃ (FIG. 2A) on         either side of that word line are set to H′ volts, by the         circuits 29 of FIG. 2B, in order to turn on the vertical TFT         select devices Q₁₂, Q₂₂, Q₃₂, Q₁₃, Q₂₃ and Q₃₃. This causes each         of the local bit lines LBL₁₂, LBL₂₂, LBL₃₂, LBL₁₃, LBL₂₃ and         LBL₃₃ in two adjacent rows extending in the x-direction to be         connected to respective ones of the global bit lines GBL1, GBL2         and GBL3. Two of the local bit lines adjacent to each other in         the y-direction are connected to a single global bit line. Those         local bit lines are then set to the zero volts of the global bit         lines. The remaining local bit lines preferably remain         unconnected and with their voltages floating.     -   3. Set the word line of the block being reset to H volts. This         reset voltage value is dependent on the switching material in         the memory element and can be between a fraction of a volt to a         few volts. All other word lines of the array, including the         other word lines of selected plane 1 and all the word lines on         the other unselected planes, are set to zero volts. In the array         of FIGS. 2A and 3, word line WL₁₂ is placed at H volts, while         all other word lines in the array are placed at zero volts, all         by the circuits 27 of FIG. 2B.

The result is that H volts are placed across each of the memory elements of the block. In the example block of FIG. 3, this includes the memory elements M₁₁₄, M₁₂₄, M₁₃₄, M₁₁₅, M₁₂₅ and M₁₃₅. For the type of memory material being used as an example, the resulting currents through these memory elements places any of them not already in a high resistance state, into that re-set state.

It may be noted that no stray currents will flow because only one word line has a non-zero voltage. The voltage on the one word line of the block can cause current to flow to ground only through the memory elements of the block. There is also nothing that can drive any of the unselected and electrically floating local bit lines to H volts, so no voltage difference will exist across any other memory elements of the array outside of the block. Therefore no voltages are applied across unselected memory elements in other blocks that can cause them to be inadvertently disturbed or reset.

It may also be noted that multiple blocks may be concurrently reset by setting any combination of word lines and the adjacent select gates to H or H′ respectively. In this case, the only penalty for doing so is an increase in the amount of current that is required to simultaneously reset an increased number of memory elements. This affects the size of the power supply that is required. In some embodiments, less than all memory elements of a block will be simultaneously reset.

The memory elements of a page are preferably programmed concurrently, in order to increase the parallelism of the memory system operation. An expanded version of the page indicated in FIG. 3 is provided in FIG. 4, with annotations added to illustrate a programming operation. The individual memory elements of the page are initially in their reset state because all the memory elements of its block have previously been reset. The reset state is taken herein to represent a logical data “1.” For any of these memory elements to store a logical data “0” in accordance with incoming data being programmed into the page, those memory elements are switched into their low resistance state, their set state, while the remaining memory elements of the page remain in the reset state.

For programming a page, only one row of select devices is turned on, resulting in only one row of local bit lines being connected to the global bit lines. This connection alternatively allows the memory elements of both pages of the block to be programmed in two sequential programming cycles, which then makes the number of memory elements in the reset and programming units equal.

Referring to FIGS. 3 and 4, an example programming operation within the indicated one page of memory elements M₁₁₄, M₁₂₄ and M₁₃₄ is described, as follows:

-   -   1. The voltages placed on the global bit lines are in accordance         with the pattern of data received by the memory system for         programming. In the example of FIG. 4, GBL₁ carries logical data         bit “1”, GBL₂ the logical bit “0” and GBL₃ the logical bit “1.”         The bit lines are set respectively to corresponding voltages M,         H and M, as shown, where the M level voltage is high but not         sufficient to program a memory element and the H level is high         enough to force a memory element into the programmed state. The         M level voltage may be about one-half of the H level voltage,         between zero volts and H. For example, a M level can be 0.7         volt, and a H level can be 1.5 volt. The H level used for         programming is not necessary the same as the H level used for         resetting or reading. In this case, according to the received         data, memory elements M₁₁₄ and M₁₃₄ are to remain in their reset         state, while memory element M₁₂₄ is being programmed. Therefore,         the programming voltages are applied only to memory element M₁₂₄         of this page by the following steps.     -   2. Set the word line of the page being programmed to 0 volts, in         this case selected word line WL₁₂. This is the only word line to         which the memory elements of the page are connected. Each of the         other word lines on all planes is set to the M level. These word         line voltages are applied by the circuits 27 of FIG. 2B.     -   3. Set one of the row select lines below and on either side of         the selected word line to the H′ voltage level, in order to         select a page for programming. For the page indicated in FIGS. 3         and 4, the H′ voltage is placed on row select line SG₂ in order         to turn on select devices Q₁₂, Q₂₂ and Q₃₂ (FIG. 1). All other         row select lines, namely lines SG₁ and SG₃ in this example, are         set to 0 volts in order to keep their select devices off. The         row select line voltages are applied by the circuits 29 of FIG.         2B. This connects one row of local bit lines to the global bit         lines and leaves all other local bit lines floating. In this         example, the row of local bit lines LBL₁₂, LBL₂₂ and LBL₃₂ are         connected to the respective global bit lines GBL₁, GBL₂ and GBL₃         through the select devices that are turned on, while all other         local bit lines (LBLs) of the array are left floating.

The result of this operation, for the example memory element material mentioned above, is that a programming current IPROG is sent through the memory element M₁₂₄, thereby causing that memory element to change from a reset state to a set (programmed) state. The same will occur with other memory elements (not shown) that are connected between the selected word line WL₁₂ and a local bit line (LBL) that has the programming voltage level H applied.

An example of the relative timing of applying the above-listed programming voltages is to initially set all the global bit lines (GBLs), the selected row select line (SG), the selected word line and two adjacent word lines on either side of the selected word line on the one page all to the voltage level M. After this, selected ones of the GBLs are raised to the voltage level H according to the data being programmed while simultaneously dropping the voltage of the selected word line to 0 volts for the duration of the programming cycle. The word lines in plane 1 other than the selected word line WL₁₂ and all word lines in the unselected other planes can be weakly driven to M, some lower voltage or allowed to float in order to reduce power that must be delivered by word line drivers that are part of the circuits 27 of FIG. 2B.

By floating all the local bit lines other than the selected row (in this example, all but LBL₁₂, LBL₂₂ and LBL₃₂), voltages can be loosely coupled to outer word lines of the selected plane 1 and word lines of other planes that are allowed to float through memory elements in their low resistance state (programmed) that are connected between the floating local bit lines and adjacent word lines. These outer word lines of the selected plane and word lines in unselected planes, although allowed to float, may eventually be driven up to voltage level M through a combination of programmed memory elements.

There are typically parasitic currents present during the programming operation that can increase the currents that must be supplied through the selected word line and global bit lines. During programming there are two sources of parasitic currents, one to the adjacent page in a different block and another to the adjacent page in the same block. An example of the first is the parasitic current I_(P1) shown on FIG. 4 from the local bit line LBL₂₂ that has been raised to the voltage level H during programming. The memory element M₁₂₃ is connected between that voltage and the voltage level M on its word line WL₁₁. This voltage difference can cause the parasitic current −I_(P1) to flow. Since there is no such voltage difference between the local bit lines LBL₁₂ or LBL₃₂ and the word line WL₁₁, no such parasitic current flows through either of the memory elements M₁₁₃ or M₁₃₃, a result of these memory elements remaining in the reset state according to the data being programmed.

Other parasitic currents can similarly flow from the same local bit line LBL₂₂ to an adjacent word line in other planes. The presence of these currents may limit the number of planes that can be included in the memory system since the total current may increase with the number of planes. The limitation for programming is in the current capacity of the memory power supply, so the maximum number of planes is a tradeoff between the size of the power supply and the number of planes. A number of 4-16 planes may generally be used in most cases, but a different amount can also be used.

The other source of parasitic currents during programming is to an adjacent page in the same block. The local bit lines that are left floating (all but those connected to the row of memory elements being programmed) will tend to be driven to the voltage level M of unselected word lines through any programmed memory element on any plane. This in turn can cause parasitic currents to flow in the selected plane from these local bit lines at the M voltage level to the selected word line that is at zero volts. An example of this is given by the currents I_(P2), I_(P3) and I_(P4) shown in FIG. 4. In general, these currents will be much less than the other parasitic current I_(P1) discussed above, since these currents flow only through those memory elements in their conductive state that are adjacent to the selected word line in the selected plane.

The above-described programming techniques ensure that the selected page is programmed (local bit lines at H, selected word line at 0) and that adjacent unselected word lines are at M. As mentioned earlier, other unselected word lines can be weakly driven to M or initially driven to M and then left floating. Alternately, word lines in any plane distant from the selected word line (for example, more than 5 word lines away) can also be left uncharged (at ground) or floating because the parasitic currents flowing to them are so low as to be negligible compared to the identified parasitic currents since they must flow through a series combination of five or more ON devices (devices in their low resistance state). This can reduce the power dissipation caused by charging a large number of word lines.

While the above description assumes that each memory element of the page being programmed will reach its desired ON value with one application of a programming pulse, a program-verify technique commonly used in NOR or NAND flash memory technology may alternately be used. In this process, a complete programming operation for a given page includes of a series of individual programming operations in which a smaller change in ON resistance occurs within each program operation. Interspersed between each program operation is a verify (read) operation that determines whether an individual memory element has reached its desired programmed level of resistance or conductance consistent with the data being programmed in the memory element. The sequence of program/verify is terminated for each memory element as it is verified to reach the desired value of resistance or conductance. After all of memory elements being programmed are verified to have reached their desired programmed value, programming of the page of memory elements is then completed.

With reference primarily to FIG. 5, the parallel reading of the states of a page of memory elements, such as the memory elements M₁₁₄, M₁₂₄ and M₁₃₄, is described. The steps of an example reading process are as follows:

-   -   1. Set all the global bit lines GBLs and all the word lines WL         to a voltage V_(R). The voltage V_(R) is simply a convenient         reference voltage and can be any number of values but will         typically be between 0 and 1 volt. In general, for operating         modes where repeated reads occur, it is convenient to set all         word lines in the array to V_(R) in order to reduce parasitic         read currents, even though this requires charging all the word         lines. However, as an alternative, it is only necessary to raise         the selected word line (WL₁₂ in FIG. 5), the word line in each         of the other planes that is in the same position as the selected         word line and the immediately adjacent word lines in all planes         to V_(R).     -   2. Turn on one row of select devices by placing a voltage on the         control line adjacent to the selected word line in order to         define the page to be read. In the example of FIGS. 2A and 5, a         voltage is applied to the row select line SG₂ in order to turn         on the vertical TFT select devices Q₁₂, Q₂₂ and Q₃₂. This         connects one row of local bit lines LBL₁₂, LBL₂₂ and LBL₃₂ to         their respective global bit lines GBL₁, GBL₂ and GBL₃. These         local bit lines are then connected to individual sense         amplifiers (SA) that are present in the circuits 21 of FIG. 2B,         and assume the potential V_(R) of the global bit lines to which         they are connected. All other local bit lines LBLs are allowed         to float.     -   3. Set the selected word line (WL₁₂) to a voltage of         V_(R)±Vsense. The sign of Vsense is chosen based on the sense         amplifier and has a magnitude of about 0.5 volt. The voltages on         all other word lines remain the same.     -   4. Sense current flowing into (V_(R)+Vsense) or out of         (V_(R)−Vsense) each sense amplifier for time T. These are the         currents I_(R1), I_(R2) and I_(R3) shown to be flowing through         the addressed memory elements of the example of FIG. 5, which         are proportional to the programmed states of the respective         memory elements M₁₁₄, M₁₂₄ and M₁₃₄. The states of the memory         elements M₁₁₄, M₁₂₄ and M₁₃₄ are then given by binary outputs of         the sense amplifiers within the circuits 21 that are connected         to the respective global bit lines GBL₁, GBL₂ and GBL₃. These         sense amplifier outputs are then sent over the lines 23 (FIG. 2)         to the controller 25, which then provides the read data to the         host 31.     -   5. Turn off the vertical TFT select devices (Q₁₂, Q₂₂ and Q₃₂)         by removing the voltage from the row select line (SG₂), in order         to disconnect the local bit lines from the global bit lines, and         return the selected word line (WL₁₂) to the voltage V_(R).

Parasitic currents during such a read operation have two undesirable effects. As with programming, parasitic currents place increased demands on the memory system power supply. In addition, it is possible for parasitic currents to exist that are erroneously included in the currents though the addressed memory elements that are being read. This can therefore lead to erroneous read results if such parasitic currents are large enough.

As in the programming case, all of the local bit lines except the selected row (LBL₁₂, LBL₂₂ and LBL₃₂ in the example of FIG. 5) are floating. But the potential of the floating local bit lines may be driven to V_(R) by any memory element that is in its programmed (low resistance) state and connected between a floating local bit line and a word line at V_(R), in any plane. A parasitic current comparable to I_(P1) in the programming case (FIG. 4) is not present during data read because both the selected local bit lines and the adjacent non-selected word lines are both at V_(R). Parasitic currents may flow, however, through low resistance memory elements connected between floating local bit lines and the selected word line. These are comparable to the currents I_(P2), I_(P3), and I_(P4) during programming (FIG. 4), indicated as I_(P5), I_(P6) and I_(P7) in FIG. 5. Each of these currents can be equal in magnitude to the maximum read current through an addressed memory element. However, these parasitic currents are flowing from the word lines at the voltage V_(R) to the selected word line at a voltage V_(R)±Vsense without flowing through the sense amplifiers. These parasitic currents will not flow through the selected local bit lines (LBL₁₂, LBL₂₂ and LBL₃₂ in FIG. 5) to which the sense amplifiers are connected. Although they contribute to power dissipation, these parasitic currents do not therefore introduce a sensing error.

Although the neighboring word lines should be at V_(R) to minimize parasitic currents, as in the programming case it may be desirable to weakly drive these word lines or even allow them to float. In one variation, the selected word line and the neighboring word lines can be pre-charged to V_(R) and then allowed to float. When the sense amplifier is energized, it may charge them to V_(R) so that the potential on these lines is accurately set by the reference voltage from the sense amplifier (as opposed to the reference voltage from the word line driver). This can occur before the selected word line is changed to V_(R)±Vsense but the sense amplifier current is not measured until this charging transient is completed.

Reference cells may also be included within the memory array 10 to facilitate any or all of the common data operations (erase, program, or read). A reference cell is a cell that is structurally as nearly identical to a data cell as possible in which the resistance is set to a particular value. They are useful to cancel or track resistance drift of data cells associated with temperature, process non-uniformities, repeated programming, time or other cell properties that may vary during operation of the memory. Typically they are set to have a resistance above the highest acceptable low resistance value of a memory element in one data state (such as the ON resistance) and below the lowest acceptable high resistance value of a memory element in another data state (such as the OFF resistance). Reference cells may be “global” to a plane or the entire array, or may be contained within each block or page.

In one embodiment, multiple reference cells may be contained within each page. The number of such cells may be only a few (less than 10), or may be up to a several percent of the total number of cells within each page. In this case, the reference cells are typically reset and written in a separate operation independent of the data within the page. For example, they may be set one time in the factory, or they may be set once or multiple times during operation of the memory array. During a reset operation described above, all of the global bit lines are set low, but this can be modified to only set the global bit lines associated with the memory elements being reset to a low value while the global bit lines associated with the reference cells are set to an intermediate value, thus inhibiting them from being reset. Alternately, to reset reference cells within a given block, the global bit lines associated with the reference cells are set to a low value while the global bit lines associated with the data cells are set to an intermediate value. During programming, this process is reversed and the global bit lines associated with the reference cells are raised to a high value to set the reference cells to a desired ON resistance while the memory elements remain in the reset state. Typically the programming voltages or times will be changed to program reference cells to a higher ON resistance than when programming memory elements.

If, for example, the number of reference cells in each page is chosen to be 1% of the number of data storage memory elements, then they may be physically arranged along each word line such that each reference cell is separated from its neighbor by 100 data cells, and the sense amplifier associated with reading the reference cell can share its reference information with the intervening sense amplifiers reading data. Reference cells can be used during programming to ensure the data is programmed with sufficient margin.

In a particular embodiment, reference cells may be used to approximately cancel parasitic currents in the array. In this case the value of the resistance of the reference cell(s) is set to that of the reset state rather than a value between the reset state and a data state as described earlier. The current in each reference cell can be measured by its associated sense amplifier and this current subtracted from neighboring data cells. In this case, the reference cell is approximating the parasitic currents flowing in a region of the memory array that tracks and is similar to the parasitic currents flowing in that region of the array during a data operation. This correction can be applied in a two-step operation (measure the parasitic current in the reference cells and subsequently subtract its value from that obtained during a data operation) or simultaneously with the data operation. One way in which simultaneous operation is possible is to use the reference cell to adjust the timing or reference levels of the adjacent data sense amplifiers.

In some conventional two-dimensional arrays of variable resistance memory elements, a diode is usually included in series with the memory element between the crossing bit and word lines. The primary purpose of the diodes is to reduce the number and magnitudes of parasitic currents during resetting (erasing), programming and reading the memory elements. A significant advantage of the three-dimensional array herein is that resulting parasitic currents are fewer and therefore have a reduced negative effect on operation of the array than in other types of arrays.

Because of the reduced number of parasitic currents in the three-dimensional array herein, the total magnitude of parasitic currents can be managed without the use of such diodes. In addition to the simpler manufacturing processes, the absence of the diodes allows bi-polar operation; that is, an operation in which the voltage polarity to switch the memory element from its first state to its second memory state is opposite of the voltage polarity to switch the memory element from its second to its first memory state. The advantage of the bi-polar operation over a unipolar operation (same polarity voltage is used to switch the memory element from its first to second memory state as from its second to first memory state) is the reduction of power to switch the memory element and an improvement in the reliability of the memory element. These advantages of the bi-polar operation are seen in memory elements in which formation and destruction of a conductive filament is the physical mechanism for switching, as in the memory elements made from metal oxides and solid electrolyte materials. For these reasons, the embodiments discussed below utilize memory elements that include resistance switching material and do not include a diode or other separate steering device. The use of memory elements that have a non-linear current versus voltage relationship are also envisioned. For example as the voltage across a HfOx memory element is reduced from the programming voltage to one half the programming voltage the current is reduced by a factor of 5 or even more. In such an embodiment the total magnitude of parasitic currents can be managed without the use of diodes in the array.

The level of parasitic currents increases with the number of planes and with the number of memory elements connected along the individual word lines within each plane. The increase in parasitic currents increases only slightly with additional planes because the selected word line is on only one plane such as WL12 in FIG. 4. Parasitic currents Ip1, Ip2, Ip3, and Ip4 are all on the plane that contains WL12. Leakage currents on other planes are less significant because the floating lines tend to minimize currents on elements not directly connected to the selected word line. Also since the number of unselected word lines on each plane does not significantly affect the amount of parasitic current, the planes may individually include a large number of word lines. The parasitic currents resulting from a large number of memory elements connected along the length of individual word lines can further be managed by segmenting the word lines into sections of fewer numbers of memory elements. Erasing, programming and reading operations are then performed on the memory elements connected along one segment of each word line instead of the total number of memory elements connected along the entire length of the word line.

The re-programmable non-volatile memory array being described herein has many advantages. The quantity of digital data that may be stored per unit of semiconductor substrate area is high. It may be manufactured with a lower cost per stored bit of data. Only a few masks are necessary for the entire stack of planes, rather than requiring a separate set of masks for each plane. The number of local bit line connections with the substrate is significantly reduced over other multi-plane structures that do not use the vertical local bit lines. The architecture eliminates the need for each memory element to have a diode in series with the resistive memory element, thereby further simplifying the manufacturing process and enabling the use of metal conductive lines. Also, the voltages necessary to operate the array are much lower than those used in current commercial flash memories.

Since at least one-half of each current path is vertical, the voltage drops present in large cross-point arrays are significantly reduced. The reduced length of the current path due to the shorter vertical component means that there are approximately one-half the number memory elements on each current path and thus the leakage currents are reduced as is the number of unselected memory elements disturbed during a data programming or read operation. For example, if there are N cells associated with a word line and N cells associated with a bit line of equal length in a conventional array, there are 2N cells associated or “touched” with every data operation. In the vertical local bit line architecture described herein, there are n cells associated with the bit line (n is the number of planes and is typically a small number such as 4 to 16), or N+n cells are associated with a data operation. For a large N this means that the number of cells affected by a data operation is approximately one-half as many as in a conventional three-dimensional array.

Materials Useful for the Memory Storage Elements

The material used for the non-volatile memory elements M_(zxy) in the array of FIG. 2A can be a chalcogenide, a metal oxide, CMO, or any one of a number of materials that exhibit a stable, reversible shift in resistance in response to an external voltage applied to or current passed through the material.

Metal oxides are characterized by being insulating when initially deposited. One suitable metal oxide is a titanium oxide (TiO_(x)) in which near-stoichiometric TiO₂ bulk material is altered in an annealing process to create an oxygen deficient layer (or a layer with oxygen vacancies) in proximity of the bottom electrode. The top platinum electrode for memory storage element comprising TiO_(x), with its high work function, creates a high potential Pt/TiO₂ barrier for electrons. As a result, at moderate voltages (below one volt), a very low current will flow through the structure. The bottom Pt/TiO_(2-x) barrier is lowered by the presence of the oxygen vacancies (O⁺ ₂) and behaves as a low resistance contact (ohmic contact). (The oxygen vacancies in TiO₂ are known to act as n-type dopant, transforming the insulating oxide in an electrically conductive doped semiconductor.) The resulting composite structure is in a non-conductive (high resistance) state.

But when a large negative voltage (such as 1.5 volt) is applied across the structure, the oxygen vacancies drift toward the top electrode and, as a result, the potential barrier Pt/TiO₂ is reduced and a relatively high current can flow through the structure. The device is then in its low resistance (conductive) state. Experiments reported by others have shown that conduction is occurring in filament-like regions of the TiO₂, perhaps along grain boundaries.

The conductive path is broken by applying a large positive voltage across the structure. Under this positive bias, the oxygen vacancies move away from the proximity of the top Pt/TiO₂ barrier, and “break” the filament. The device returns to its high resistance state. Both of the conductive and non-conductive states are non-volatile. Sensing the conduction of the memory storage element by applying a voltage around 0.5 volts can easily determine the state of the memory element.

While this specific conduction mechanism may not apply to all metal oxides, as a group, they have a similar behavior: transition from a low conductive state to a high conductive occurs state when appropriate voltages are applied, and the two states are non-volatile. Examples of other materials that can be used for the non-volatile memory elements M_(zxy) in the array of FIG. 2A include HfOx, ZrOx, WOx, NiOx, CoOx, CoAlOx, MnOx, ZnMn₂O₄, ZnOx, TaOx, NbOx, HfSiOx, HfAlOx. Suitable top electrodes include metals with a high work function (typically >4.5 eV) capable to getter oxygen in contact with the metal oxide to create oxygen vacancies at the contact. Some examples are TaCN, TiCN, Ru, RuO, Pt, Ti rich TiOx, TiAlN, TaAlN, TiSiN, TaSiN, IrO₂ and doped polysilicon. Suitable materials for the bottom electrode are any conducting oxygen rich material such as Ti(O)N, Ta(O)N, TiN and TaN. The thicknesses of the electrodes are typically 1 nm or greater. Thicknesses of the metal oxide are generally in the range of 2 nm to 20 nm.

One example non-volatile memory element uses Hafnium Oxide (e.g., HfO₂) as a reversible resistance-switching material, and positions the reversible resistance-switching material between two electrodes. A first electrode is positioned between reversible resistance-switching material and a first conductor (e.g. bit line or word line). In one embodiment, the first electrode is made of platinum. The second electrode is positioned between reversible resistance-switching material a second conductor (e.g, bit line or word line). In one embodiment, the second electrode is made of Titanium Nitride, and serves as a barrier layer. In another embodiment, the second electrode is n+ doped polysilicon and the first electrode is Titanium Nitride. Other materials can also be used. The technologies described below are not restricted to any one set of materials for forming the non-volatile memory elements.

In another embodiment, the memory storage element will include Hafnium Oxide (or different metal oxide or different material) as the reversible resistance-switching material, without any electrodes being positioned between the reversible resistance-switching material and the conductors (e.g., bit lines and/or word lines).

Another class of materials suitable for the memory storage elements is solid electrolytes but since they are electrically conductive when deposited, individual memory elements need to be formed and isolated from one another. Solid electrolytes are somewhat similar to the metal oxides, and the conduction mechanism is assumed to be the formation of a metallic filament between the top and bottom electrode. In this structure the filament is formed by dissolving ions from one electrode (the oxidizable electrode) into the body of the cell (the solid electrolyte). In one example, the solid electrolyte contains silver ions or copper ions, and the oxidizable electrode is preferably a metal intercalated in a transition metal sulfide or selenide material such as A_(x)(MB2)_(1-x), where A is Ag or Cu, B is S or Se, and M is a transition metal such as Ta, V, or Ti, and x ranges from about 0.1 to about 0.7. Such a composition minimizes oxidizing unwanted material into the solid electrolyte. One example of such a composition is Ag_(x)(TaS2)_(1-x). Alternate composition materials include α-AgI. The other electrode (the indifferent or neutral electrode) should be a good electrical conductor while remaining insoluble in the solid electrolyte material. Examples include metals and compounds such as W, Ni, Mo, Pt, metal silicides, and the like.

Examples of solid electrolytes materials are: TaO, GeSe or GeS. Other systems suitable for use as solid electrolyte cells are: Cu/TaO/W, Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W, and Ag/GeS/W, where the first material is the oxidizable electrode, the middle material is the solid electrolyte, and the third material is the indifferent (neutral) electrode. Typical thicknesses of the solid electrolyte are between 30 nm and 100 nm.

In recent years, carbon has been extensively studied as a non-volatile memory material. As a non-volatile memory element, carbon is usually used in two forms, conductive (or grapheme like-carbon) and insulating (or amorphous carbon). The difference in the two types of carbon material is the content of the carbon chemical bonds, so called sp² and sp³ hybridizations. In the sp³ configuration, the carbon valence electrons are kept in strong covalent bonds and as a result the sp³ hybridization is non-conductive. Carbon films in which the sp³ configuration dominates, are commonly referred to as tetrahedral-amorphous carbon, or diamond like. In the sp² configuration, not all the carbon valence electrons are kept in covalent bonds. The weak tight electrons (phi bonds) contribute to the electrical conduction making the mostly sp² configuration a conductive carbon material. The operation of the carbon resistive switching nonvolatile memories is based on the fact that it is possible to transform the sp³ configuration to the sp² configuration by applying appropriate current (or voltage) pulses to the carbon structure. For example, when a very short (1-5 ns) high amplitude voltage pulse is applied across the material, the conductance is greatly reduced as the material sp² changes into an sp³ form (“reset” state). It has been theorized that the high local temperatures generated by this pulse causes disorder in the material and if the pulse is very short, the carbon “quenches” in an amorphous state (sp³ hybridization). On the other hand, when in the reset state, applying a lower voltage for a longer time (˜300 nsec) causes part of the material to change into the sp² form (“set” state). The carbon resistance switching non-volatile memory elements have a capacitor like configuration where the top and bottom electrodes are made of high temperature melting point metals like W, Pd, Pt and TaN.

There has been significant attention recently to the application of carbon nanotubes (CNTs) as a non-volatile memory material. A (single walled) carbon nanotube is a hollow cylinder of carbon, typically a rolled and self-closing sheet one carbon atom thick, with a typical diameter of about 1-2 nm and a length hundreds of times greater. Such nanotubes can demonstrate very high conductivity, and various proposals have been made regarding compatibility with integrated circuit fabrication. It has been proposed to encapsulate “short” CNT's within an inert binder matrix to form a fabric of CNT's. These can be deposited on a silicon wafer using a spin-on or spray coating, and as applied the CNT's have a random orientation with respect to each other. When an electric field is applied across this fabric, the CNT's tend to flex or align themselves such that the conductivity of the fabric is changed. As in the other carbon based resistive switching non-volatile memories, the CNT based memories have capacitor-like configurations with top and bottom electrodes made of high melting point metals such as those mentioned above.

Yet another class of materials suitable for the memory storage elements is phase-change materials. A preferred group of phase-change materials includes chalcogenide glasses, often of a composition Ge_(x)Sb_(y)Te_(z), where preferably x=2, y=2 and z=5. GeSb has also been found to be useful. Other materials include AgInSbTe, GeTe, GaSb, BaSbTe, InSbTe and various other combinations of these basic elements. Thicknesses are generally in the range of 1 nm to 500 nm. The generally accepted explanation for the switching mechanism is that when a high energy pulse is applied for a very short time to cause a region of the material to melt, the material “quenches” in an amorphous state, which is a low conductive state. When a lower energy pulse is applied for a longer time such that the temperature remains above the crystallization temperature but below the melting temperature, the material crystallizes to form poly-crystal phases of high conductivity. These devices are often fabricated using sub-lithographic pillars, integrated with heater electrodes. Often the localized region undergoing the phase change may be designed to correspond to a transition over a step edge, or a region where the material crosses over a slot etched in a low thermal conductivity material. The contacting electrodes may be any high melting metal such as TiN, W, WN and TaN in thicknesses from 1 nm to 500 nm.

It will be noted that the memory materials in most of the foregoing examples utilize electrodes on either side thereof whose compositions are specifically selected. In embodiments of the three-dimensional memory array herein where the word lines (WL) and/or local bit lines (LBL) also form these electrodes by direct contact with the memory material, those lines are preferably made of the conductive materials described above. In embodiments using additional conductive segments for at least one of the two memory element electrodes, those segments are therefore made of the materials described above for the memory element electrodes.

Steering elements are commonly incorporated into controllable resistance types of memory storage elements. Steering elements can be a transistor or a diode. Although an advantage of the three-dimensional architecture described herein is that such steering elements are not necessary, there may be specific configurations where it is desirable to include steering elements. The diode can be a p-n junction (not necessarily of silicon), a metal/insulator/insulator/metal (MIIM), or a Schottky type metal/semiconductor contact but can alternately be a solid electrolyte element. A characteristic of this type of diode is that for correct operation in a memory array, it is necessary to be switched “on” and “off” during each address operation. Until the memory element is addressed, the diode is in the high resistance state (“off” state) and “shields” the resistive memory element from disturb voltages. To access a resistive memory element, three different operations are needed: a) convert the diode from high resistance to low resistance, b) program, read, or reset (erase) the memory element by application of appropriate voltages across or currents through the diode, and c) reset (erase) the diode. In some embodiments one or more of these operations can be combined into the same step. Resetting the diode may be accomplished by applying a reverse voltage to the memory element including a diode, which causes the diode filament to collapse and the diode to return to the high resistance state.

For simplicity the above description has considered the simplest case of storing one data value within each cell: each cell is either reset or set and holds one bit of data. However, the techniques of the present application are not limited to this simple case. By using various values of ON resistance and designing the sense amplifiers to be able to discriminate between several of such values, each memory element can hold multiple-bits of data in a multiple-level cell (MLC). Structural Example of the Three-Dimensional Array

One example semiconductor structure for implementing the three-dimensional memory element array of FIG. 2A is illustrated in FIG. 6, which is configured for use of non-volatile memory element (NVM) material that is non-conductive when first deposited. A metal oxide of the type discussed above has this characteristic. Since the material is initially non-conductive, there is no necessity to isolate the memory elements at the cross-points of the word and bit lines from each other. Several memory elements may be implemented by a single continuous layer of material, which in the case of FIG. 6 are strips of NVM material oriented vertically along opposite sides of the vertical bit lines in the y-direction and extending upwards through all the planes. A significant advantage of the structure of FIG. 6 is that all word lines and strips of insulation under them in a group of planes may be defined simultaneously by use of a single mask, thus greatly simplifying the manufacturing process.

Referring to FIG. 6, a small part of four planes 101, 103, 105 and 107 of the three-dimensional array are shown. Elements of the FIG. 6 array that correspond to those of the equivalent circuit of FIG. 2A are identified by the same reference numbers. It will be noted that FIG. 6 shows the two planes 1 and 2 of FIG. 2A plus two additional planes on top of them. All of the planes have the same horizontal pattern of conductor, dielectric and NVM material. In each plane, metal word lines (WL) are elongated in the x-direction and spaced apart in the y-direction. Each plane includes a layer of insulating dielectric that isolates its word lines from the word lines of the plane below it or, in the case of plane 101, of the substrate circuit components below it. Extending through each plane is a collection of metal local bit line (LBL) “pillars” elongated in the vertical z-direction and forming a regular array in the x-y direction.

Each bit line pillar is connected to one of a set of global bit lines (GBL) running in the y-direction at the same pitch as the pillar spacing through the vertical TFT select devices (Q_(xy)) whose gates are driven by the row select lines (SG) elongated in the x-direction. The vertical TFT select devices have a tunnel barrier, in one embodiment.

Not shown in FIG. 6 are sense amplifiers, input-output (I/O) circuitry, control circuitry, and any other necessary peripheral circuitry. There is one row select line (SG) for each row of local bit line pillars in the x-direction and one vertical TFT select device (Q) for each individual vertical local bit line (LBL).

Each vertical strip of NVM material is sandwiched between the vertical local bit lines (LBL) and a plurality of word lines (WL) vertically stacked in all the planes. Preferably the NVM material is present between the local bit lines (LBL) in the x-direction. A memory storage element (M) is located at each intersection of a word line (WL) and a local bit line (LBL). In the case of a metal oxide described above for the memory storage element material, a small region of the NVM material between an intersecting local bit line (LBL) and word line (WL) is controllably alternated between conductive (set) and non-conductive (reset) states by appropriate voltages applied to the intersecting lines.

In one embodiment, the NVM material includes Hafnium Oxide, the word lines comprise TiN, and the bit lines comprise N+ silicon.

There may also be a parasitic NVM element formed between the LBL and the dielectric between planes. By choosing the thickness of the dielectric strips to be large compared to the thickness of the NVM material layer (that is, the spacing between the local bit lines and the word lines), a field caused by differing voltages between word lines in the same vertical word line stack can be made small enough so that the parasitic element never conducts a significant amount of current. Similarly, in other embodiments, the non-conducting NVM material may be left in place between adjacent local bit lines if the operating voltages between the adjacent LBLs remain below the programming threshold.

To enable the memory to be denser (e.g., more memory elements per area), the size of the memory elements can be made small and the memory elements can be arranged close to each. To enable the memory elements to be close to each other, one embodiment uses a vertically oriented TFT selector (or decoder) for connecting the individual local vertical bit line pillars to the respective global bit lines. In one embodiment, each vertically oriented TFT select device is a pillar select device that is formed as a vertical structure, switching between a local bit line pillar and a global bit line. The vertical TFT select devices, are in the present embodiments formed in a separate layer (pillar select layer) above the CMOS layer/substrate, along the z-direction between the array of global bit lines and the array of local bit lines. The CMOS layer is the substrate where the support circuitry is implemented, including the row select circuit and word line drivers. The use of vertically oriented TFT select devices above, but not in, the substrate allows the memory elements to be arranged in a more compact fashion, thereby increasing density. Additionally, positioning the vertically oriented TFT select devices above the substrate allows for other devices (e.g., the word line drivers) to be positioned in the substrate under the memory array rather than outside of the array, which allows the integrated circuit to be smaller.

For example, a pillar shaped vertical Thin Film Transistor (TFT) can be can be used as the select device. In one example implementation, a control node of the select transistor has a collar shaped hole, and the gate and channel region are formed in the hole with the source/drain regions formed above/below the channel region. Another alternative is to define the gates as a rail etch and have the channel deposited in a trench between the gates and singulated by an etch with crossing lines mask (rather than holes).

FIG. 7 illustrates schematically the three dimensional memory (“3D memory”) comprising of a memory layer on top of a pillar select layer. The 3D memory 10 is formed on top of a CMOS substrate (not shown explicitly) where structures in the CMOS are referred to as being in the FEOL (“Front End of Lines”). The vertically oriented TFT select devices switching individual vertical bit lines (that are above and not in the substrate) to individual global bit lines are now formed on top of the FEOL layer in the BEOL (“Back End of Lines”). Thus, the BEOL comprises of the pillar select layer with the memory layer on top of it. The vertically oriented TFT select devices (such as Q₁₁, Q₁₂, . . . , Q₂₁, Q₂₂, . . . , etc.) are formed in the pillar select layer as vertically oriented TFT select devices. The pillar select layer is formed above (and not in) the substrate. The memory layer comprises multiple layers of word lines and memory elements. For simplicity, FIG. 7 shows only one layer of word lines, such as WL₁₀, W₁₁, . . . , etc without showing the memory elements that exist between each crossing of a word line and a bit line.

In the example of FIG. 7, the vertically oriented TFT select devices have one gate that is connected to one of the select lines. In some embodiments, each vertically oriented TFT select device has two gates.

FIG. 8A illustrates a schematic circuit diagram of a given vertically oriented TFT select device switching a local bit line to a global bit line. In the example, the local bit line LBL 530 is switchable to the global bit line GBL 526 by a vertically oriented TFT select transistor 504 such as Q₁₁. The gate of the TFT select transistor Q₁₁ is controllable by a signal exerted on a row select line SG₁.

FIG. 8B illustrates the structure of the vertically oriented TFT select device 504 in relation to the local bit line and the global bit line. The global bit line such as GBL 526 is formed below the vertically oriented TFT select device 504, in the FEOL as part of the metal layer-1 or metal layer-2. The vertically oriented TFT select device 504 is formed in the BEOL layer on top of the GBL 526 (and above, but not in, the substrate). The local bit line LBL 530, in the form of a pillar, is formed on top of the vertically oriented select device 504. In this way, the vertically oriented TFT select device 504 can switch the local bit line pillar LBL to the global bit line GBL.

FIG. 9 shows a portion of the memory system, with the memory elements being depicted as resistors (due to their reversible resistance switching properties). FIG. 9 shows the Pillar Select Layer below the Memory Layer and above (and not in) the Substrate. Only a portion of the Memory Layer is illustrated. For example, FIG. 9 shows bit lines LBL1, LBL2, . . . LBL72. In this embodiment each of the word lines are connected to 72 memory elements. Each of the memory elements is connected between a word line and a bit line. Therefore, there will be 72 memory elements connected to the same word line and different bit lines (of the 72 bit lines in a row). Each of the bit lines are connected to a respective global bit line by one of the vertically oriented TFT select devices 504 of the Pillar Select Layer. The signal SG_(x) driving the set of vertically oriented TFT select devices 504 depicted in FIG. 9 is controlled by the Row Select Line Driver. Note that the Row Select Line Driver is implemented in the substrate. The global bit lines (GBL1, GBL2, . . . GBL72) are implemented in the metal lines above the substrate. FIG. 9 shows one slice taken along the word line direction such that each of the bit lines depicted in FIG. 9 are connected to different global bit lines via the vertically oriented TFT select devices 504.

In one embodiment, pairs of neighboring word lines (e.g., WLa and WLb, WLp and WLq, WLr and WLs) will be connected to memory elements that are in turn connected to common bit lines. FIG. 9 shows three pairs of word lines (WLa and WLb, WLp and WLq, WLr and WLs), with each of the pair being on a different layer of the memory structure. In one illustrative embodiment, the word lines receive address dependent signals such a that word line WLb is selected for memory operation while word lines WLa, WLp, WLq, WLr and WLs are not selected. Although the enabling signal applied on row select line SGx causes all of the vertically oriented TFT select devices 504 to connect the respective global bit lines to the respective local bit lines of FIG. 9, only the global bit line GLBL1 includes a data value for programming (as noted by the S). Global bit lines GLBL2 and GLBL72 do not include data for programming (as noted by the U). This can be due to the data pattern being stored as the global bit lines receive data dependent signals. Note that while SGx receive an enable signal, other select lines receive a disable signal to turn off the connected select devices.

Because local bit line LBL 1 and word line WLb are both selected for programming, the memory element between local bit line LBL1 and word line WLb is selected for the memory operation (as noted by the S). Since local bit line LBL1 is the only bit line with program data, the other memory elements connected to WLb will be half selected (as noted by H). By half selected, it is meant that one of the control lines (either the bit line or the word line) is selected but the other control line is not selected. A half selected memory element will not undergo the memory operation. The word line WLa is not selected; therefore, the memory cell between WLa and local bit line LBL1 is half selected, and the other memory elements on WLa are unselected. Since word lines WLp, WLq, WLr and WLs are not selected, their memory elements connected to LBL1 are half selected and the other memory elements connected to those word lines are unselected.

FIGS. 10A-10D depict various embodiments of vertical TFT selection devices 504. In FIG. 10A, the TFT 504 is an N+/P−/N+ device with the tunnel barrier 509 at the junction between the first (or lower) source/drain region 501 a and channel region 502. In FIG. 10B, the TFT 504 is a P+/N−/P+ device with the tunnel barrier 509 at the junction between the first source/drain region 501 a and channel region 502. FIG. 10C, the TFT 504 is an N+/P−/N+ device with the tunnel barrier 509 at the junction between the second (or upper) source/drain region 501 b and channel region 502. In FIG. 10D, the TFT 504 is a P+/N−/P+ device with the tunnel barrier 509 at the junction between the second source/drain region 501 b and channel region 502. Note that the channel region 502 of each of these devices 504 could be lightly doped or intrinsic.

The lower conductor 514 in any of FIGS. 10A-10D is a global bit line 526, in one embodiment. The upper conductor 516 in any of FIGS. 10A-10D is a local vertical bit line 530, in one embodiment. Thus, the TFTs in any of FIGS. 10A-10D could be used in memory arrays having vertical bit lines.

FIG. 11A is a cross-sectional view of a memory structure using one embodiment of a vertically oriented TFT select device 504 and the memory structure of FIG. 6. In one embodiment, the gate dielectric 505 extends along the sides of the source/drain regions 501 and the channel 502. The vertical TFT selection device 504 has two gates 507 in this embodiment. However, the vertical TFT selection device 504 could have a single gate. An insulator 519, such as silicon oxide, separates the gates 507 of two neighboring TFTs 504. The gate dielectric separates the gates from either the channel region 502 or the source/drain 501, as the case may be.

The lower source/drain 501 a is electrically connected to a global bit line 526 in this embodiment. The global bit line has a metal portion 526 a and a polysilicon portion 526 b in this embodiment. There may be a material that is physically between the lower source/drain 501 a and the global bit line 526, such as titanium or titanium nitride.

The upper source/drain 501 b is electrically connected to a vertical bit line 530 in this embodiment. The vertical bit line 530 is formed from polysilicon in one embodiment. In another embodiment, the vertical bit line 530 is formed from metal, such as tungsten. There may be a material that is physically between the upper source/drain 501 b and the vertical bit line 530, such as titanium or titanium nitride.

The tunnel barrier 509 helps provide for good high voltage operation. The vertical TFT select devices 504 are able to withstand high voltage differences between their source/drain regions 501 a, 501 b. For some operations, a relatively high voltage difference results between the two source/drains 501 a, 501 b. It is important that the vertically oriented TFT select device 504 does not breakdown. The tunnel barrier 509 results in higher breakdown voltage, which can prevent breakdown during required high voltage operation. The tunnel barrier 509 can also result in much lower leakage during high voltage operation, which is important for the proper cell and array operation.

It is also important that the TFT 504 does not exhibit high leakage. The tunnel barrier 509 also helps provide for a low leakage current. Note that GIDL could possibly be a problem when operating the vertically oriented TFT select device 504. However, the tunnel barrier 509 helps noticeably reduce or minimize GIDL.

Note that the vertical bit line material may serve as one of the electrodes of read-write memory elements. In some embodiments, the material of the vertical bit line 530 is N+ polysilicon. For some types of memory cells, N+ polysilicon serves as a better electrode choice (on the BL side) to achieve desired operation of a specific memory cell and memory array. In one embodiment, the upper source drain 501 b is N+ when the vertical bit line is N+. Similarly, the polysilicon portion of the global bit line 526 b and the lower source drain 501 a may each be N+.

However, for other memory cells with different material composition, P+ polysilicon may be a better choice as an electrode (on bit line side) to ensure desired operation of the memory cell and array. This may be due to the fact that P+ polysilicon work function is different from N+ polysilicon, and may be more suitable for the electrode material to enable the most efficient memory cell operation. In this latter case, a PFET TFT selection device may be preferable due to its source/drain being P+(thus matching the vertical bit line). Thus, in one embodiment, the upper source drain 501 b is P+ when the vertical bit line is P+. Similarly, the polysilicon portion of the global bit line 526 b and the lower source drain 501 a may each be P+.

The memory layer includes a set of vertical bit lines 530 (comprising N+ polysilicon). Interspersed between the vertical bit lines 530 are alternating oxide layers 534 and word line layers 536. In one embodiment, the word lines are made from TiN. Between the vertical bit lines 530 and the stacks of alternating oxide layers 536 and word line layers 536 are vertically oriented layers of reversible resistance switching material 532. In one embodiment, the reversible resistance switching material is made of Hafnium Oxide HfO₂. However, other materials (as described above) can also be used. Box 540 depicts one example memory element which includes the reversible resistance switching material 532 sandwiched between a word line 536 and vertical bit line 530. The memory elements are positioned above, and not in, the substrate.

As described below, the memory structure of FIG. 11A is a continuous mesh array of memory elements because there are memory elements connected to both sides of the bit lines and memory elements connected to both sides of the word lines. At the bottom of FIG. 11A, the CMOS substrate is depicted. Implemented on the top surface of the CMOS structure are various metal lines including ML-0, ML-1, and ML-2. Line 526 of ML-2 serves as a respective global bit line (GBL). This is divided between a metal layer 526 a and a polysilicon layer 526 b. The Pillar Select Layer includes oxide region 519 separating the gate material layer 507. The oxide 519 can be Sift. The metal line ML-2 526 a serving as at least a portion of the global bit line can be implemented of any suitable material, including Tungsten, or Tungsten on a Titanium Nitride adhesion layer or a sandwich of n+ polysilicon on Tungsten on Titanium Nitride adhesion layer. Gate material 507 can be polysilicon, Titanium Nitride, Tantalum Nitride, Nickel Silicide or any other suitable material. Gate material 507 implements the row select lines SG_(x) (e.g. SG₁, SG₂, . . . of FIG. 2A), which are labeled in FIG. 11A as row select lines 507. Portions of the row select lines may also be referred to a transistor gates.

FIG. 11B is a cross-sectional view of another embodiment of a memory structure using the vertically oriented TFT select device 504. In this example, the gates 507 have a different shape relative to the embodiment of FIG. 11A. FIG. 11B shows six row select lines (SG_(x)) 507, each underneath a stack of multiple word lines. As can be seen, each of the row select lines 507 is positioned between two vertically oriented select devices 504, above and not in the substrate. Therefore each row select line can serve as the gate signal to either of the two neighboring vertically oriented TFT select devices 504; therefore, the vertically oriented TFT select devices 504 are said to be double gated. Each vertically oriented TFT select device 504 can be controlled by two different row select lines, in this embodiment. In FIG. 11B, the pillar select layer has two oxide regions 520, 521 adjacent to each TFT 504.

Note that although the tunnel barrier 509 in the example of FIGS. 11A and 11B is by the lower source/drain region 501 a, another option is to place the tunnel barrier 509 between the channel 502 and the upper source/drain 501 b.

FIG. 12 is a partial schematic of the memory system of FIGS. 11A and 11B depicting the above-described double-gated structure for the vertically oriented TFT select devices 504. Planes 1 and 2 of FIG. 12 are the same as in FIG. 2A. As can be seen, each local bit line LBL is connectable to a respective global bit line GBL by two row select signals. FIG. 12 shows two transistors connecting to each local bit line. For example, transistor Q₁₁ can connect local bit line LBL₁₁ to global bit line GBL₁ in response to row select line SG₁ and transistor Qua can connect local bit line LBL₁₁ to global bit line GBL₁ in response to row select line SG₂. The same structure is used for the other local bit lines depicted in FIG. 13.

FIG. 13 shows another partial schematic also depicting the double-gated structure such that each local bit line (LBL1, LBL2, . . . LBL72) are connected to their respective global bit lines (GBL1, GBL2, . . . GBL72) by any of two respective vertically oriented TFT select devices that are positioned above the CMOS substrate. As can be seen, while the double-gated structure includes positioning the various select devices 504 above the substrate, the Row Select Line Drivers providing the row select lines SG₁, SG₂, . . . are positioned in the substrate. Similarly, the global word lines (e.g., GWL) are position in a metal layer on the substrate and below the vertically oriented select devices. Furthermore, as will be explained below, in one embodiment the Row Select Line Driver uses the appropriate global word line GWL as an input.

FIG. 14 is a flow chart describing one embodiment for manufacturing a 3D memory device having a vertical TFT select device 504 with a tunnel barrier 509. This process may be used to form a 3D memory device depicted similar to the one depicted in FIG. 11A. In this embodiment, the vertical TFT selection devices 504 have their tunnel barrier 509 at the lower source/drain region 501 a. Note that other processes can be used form the vertical TFT select device 504. In FIG. 14, the TFT is an embodiment that is N+/p−/N+. The process can be modified for other devices such as, for example, P+/n−/P. Also note that the channel region 502 is not required to be intentionally doped.

This process can be performed after manufacturing the metal layers and substrate layers (e.g., drivers and other logic), and before manufacturing the memory layer. The substrate layers, metal layers and memory layers can be manufactured using other processes known and/or described elsewhere. In step 600, the global bit lines are formed. In step 602, a layer of titanium nitride (TiN) is deposited over the global bit lines.

In step 604, a first n+ silicon layer is formed over the titanium nitride layer. The n+ silicon may be doped in situ or after depositing the silicon with an n-type dopant such as phosphorous or arsenic. This will be for the lower source/drain region 501 a.

In step 606, a layer for the tunnel barrier is formed over the n+ silicon. The tunnel barrier material is formed by Atomic Layer Deposition (ALD), in one embodiment. This material is an insulator in one embodiment. The material is a dielectric, in one embodiment. In one embodiment, a layer of silicon oxide is formed. In one embodiment, a layer of hafnium oxide is formed. The tunnel barrier layer is kept relatively thin in one embodiment. As one example, the tunnel barrier layer is about 3.5 nm or thinner. It is possible to thermally grow a thin layer of, for example, silicon oxide. However, ALD may provide better control of the thickness.

In step 608, a p− silicon layer is formed over the tunnel barrier layer. In one embodiment, this layer is formed by lightly doping the silicon either in situ or after depositing the silicon with a p-type dopant, such as boron. In one embodiment, this layer is not intentionally doped. This layer will be for the channel region 502.

In step 610, a second n+ silicon layer is formed over the p− silicon layer. The n+ silicon may be doped in situ or after depositing the silicon with an n-type dopant such as, phosphorous or arsenic. This will be for the upper source/drain region 501 b.

In step 611, another layer of titanium nitride is formed over the second n+ silicon layer.

FIG. 15A depicts results after step 611 showing the global bit line 526 comprising a metal layer 526 a and an n+ polysilicon layer 526 b, a first TiN layer 1502, lower n+ layer 1504, tunnel barrier layer 1506, p− layer 1508, upper n+ layer 1510, and second TiN layer 1512. In one embodiment, intrinsic silicon is deposited for both layers 1508 and 1510. Then, the upper n+ layer 1510 is formed by implanting a dopant using a suitable energy level. However, intentional p− doping could be employed for layer 1508.

Note that the tunnel barrier layer 1506 may act as a diffusion barrier during device fabrication in that it can prevent diffusion of dopants from the lower n+ layer 1504 into the p-layer 1508. In other words, it can prevent diffusion of dopants from the region that is being doped to form one of the source/drain regions 501 into the region that is either not intentional doped (or lightly doped) that will serve as the channel region 502. This can allow the doping level in what will become the channel region 502 to be more precisely controlled. This can also allow for lower (or no doping) to be used in the region that will become the channel region 502. Better control of the doping concentration in the channel region 502 can help to reduce the overall height of the TFT 504.

In step 612, etching is performed to form pillars for the vertical TFT selected devices. FIG. 15B depicts results after step 612, showing several pillars 1525. Each pillar 1525 has first TiN region 1552, lower source/drain region 501 a (n+ in this example), tunnel barrier 509, channel region 502 (p− in this example), upper source/drain region 501 b (n+ in this example), and second TiN region 1554.

In step 614, a gate dielectric is formed. FIG. 15C depicts results after step 614 showing the gate dielectric material 1528 over the pillars 1525. At this stage a portion of the material 1528 for the gate dielectric may still be in place on the tops of the pillars 1525. However, this will be removed later. In one embodiment, the gate dielectric material 1528 is formed by ALD of silicon oxide. In one embodiment, the gate dielectric material 1528 is formed by ALD of hafnium oxide. In one embodiment, the gate dielectric material 1528 is thermally grown oxide. In one example implementation, the gate dielectric layer 1528 will be approximately 3 to 10 nanometers thick.

In step 616, material is deposited for the gates. In one embodiment, TiN is deposited. In one embodiment, silicon is deposited. In step 618, the gate material is etched to form the gates. For example, reactive ion etching (RIE) is used. FIG. 15D depicts results after step 618, showing gates 507. In this embodiment, each TFT has two gates 507. In another embodiment, a TFT has a single gate. In one embodiment, the gate material (e.g., TiN) is deposited over the gate dielectric 1528 in a more or less conformal layer.

In step 620, another layer of oxide is formed. For example, CVD can be used to deposit Sift. In step 622, the oxide is etched back. FIG. 15E depicts results after step 622, showing oxide layer 519. At this point the portion of the gate dielectric material that was above the pillars 1525 has been removed.

In step 624, vertical bit lines are formed. Also, other elements in the memory layer may also be formed. FIG. 11A shows an example of results after step 624. Note that the first and second TiN regions 1552, 1554 are not depicted in FIG. 11A.

In one embodiment, a vertical TFT 504 having a tunnel barrier is used as a selection device in a 3D vertical NAND memory array. The vertical TFT 504 is located between a common source line and a NAND string channel, in one embodiment.

A NAND structure includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 16 is a circuit representation of a NAND string. The NAND string depicted in FIG. 16 includes four transistors 1600, 1602, 1604 and 1606 in series and sandwiched between (drain side) select gate 1620 and (source side) select gate 1622. Select gate 1620 connects the NAND string to a bit line 1611. Select gate 1622 connects the NAND string to source line 1628. Select gate 1620 is controlled by applying the appropriate voltages to select line SGD. Select gate 1622 is controlled by applying the appropriate voltages to select line SGS. In one embodiment, select gate 1622 is implemented with a vertical TFT having a tunnel barrier.

Each of the transistors 1600, 1602, 1604 and 1606 has a control gate (CG) and a charge storage region (CTR). For example, transistor 1600 has control gate 1600CG charge storage region 1600CTR. Transistor 1602 includes control gate 1602CG and a 1600CG charge storage region 1602CTR. Transistor 1604 includes control gate 1604CG and 1600CG charge storage region 1604CTR. Transistor 1606 includes a control gate 1606CG and a 1600CG charge storage region 1606CTR. Control gate 1600CG is connected to word line WL3, control gate 1602CG is connected to word line WL2, control gate 1604CG is connected to word line WL1, and control gate 1606CG is connected to word line WL0.

Note that although FIG. 16 shows four memory cells in the NAND string, the use of four memory cells is only provided as an example. A NAND string can have fewer than four memory cells or more than four memory cells. The discussion herein is not limited to any particular number of memory cells in a NAND string. One embodiment uses NAND strings with some memory cells are used to store data and one or more of the memory cells are referred to as dummy memory cells because they do not store data.

A typical architecture for a flash memory system using a NAND structure will include several NAND strings. Each NAND string is connected to the common source line by its source select gate controlled by select line SGS and connected to its associated bit line by its drain select gate controlled by select line SGD. Bit lines may be shared with multiple NAND strings. The bit line may be connected to a sense amplifier.

The charge storage region (CTR) may utilize a non-conductive dielectric material to store charge in a non-volatile manner. In one embodiment, a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride.

The following discussion of an example 3D memory device is presented as one possible architecture in which one embodiment of a vertical TFT 504 having a tunnel barrier may be used. FIG. 17 is a perspective view of a 3D stacked non-volatile memory device. The 3D memory device 1700 includes a substrate 1701. In one embodiment, the substrate 1701 is formed from silicon. On the substrate are example blocks BLK0 and BLK1 of memory cells and a peripheral area 1706 with circuitry for use by the blocks. The substrate 1701 can also carry circuitry under the blocks, along with one or more lower metal layers which are patterned in conductive paths to carry signals of the circuitry. The blocks are formed in an intermediate region 1702 of the memory device. The circuitry associated with operation of the memory cells may be above or within the substrate 1701. In one embodiment, the non-volatile memory device is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above the substrate 1701.

In an upper region 1703 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block comprises a stacked area of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block has opposing tiered sides from which vertical contacts extend upward to an upper metal layer to form connections to conductive paths. While two blocks are depicted as an example, additional blocks can be used, extending in the x- and/or y-directions.

In one possible approach, the length of the plane, in the x-direction, represents a direction in which signal paths to word lines extend in the one or more upper metal layers, and the width of the plane, in the y-direction, represents a direction in which signal paths to bit lines extend in the one or more upper metal layers. The z-direction represents a height of the memory device.

In one embodiment, NAND strings have a straight shape. FIG. 18 depicts an embodiment of block BLK0 of FIG. 17 which includes straight NAND strings. The block BLK0B includes straight NAND strings arranged in sets (SetB0, SetB1, SetB2, SetB3, . . . , SetBn, where there are n−1 sets in a block). Each set of NAND strings is associated with one bit line (BLB0, BLB1, BLB2, BLB3, . . . , BLBn). In one embodiment, each NAND string has a drain side select gate that is able to connect/disconnect the NAND string from its bit line. The drain side select gates in a set of NAND strings may be individually selectable, such that one NAND string in the set may be selected at a given time. In one approach, all NAND strings in a block which are associated with one bit line are in the same set. Each straight NAND string has one column of memory cells. For example, SetA0 includes NAND strings NSB0, NSB1, NSB2, NSB3, NSB4 and NSB5. Source lines extend parallel to the bit line and include SLB0, SLB1, SLB2, SLB3, . . . , SLBn. In one approach, the source lines in a block are joined to one another and driven by one driver. The bit lines are above the memory cell array and the source lines are below the memory cell array in this example.

FIG. 19 depicts a cross-sectional view of a block of the 3D non-volatile memory device of FIG. 18 having straight strings. The view of a portion of setB0 of NAND strings of FIG. 18. Columns of memory cells corresponding to NAND strings NSB0 to NSB5, respectively, are depicted in the multi-layer stack. The stack 1977 includes a substrate 1701, an insulating film 1909 on the substrate, and a portion of a source line SLB1. Additional straight NAND strings in a sub-block extend in front of and in back of the NAND strings depicted in the cross-section, e.g., along the x-axis. The NAND strings NSB0 to NSB5 are each in a different sub-block, but are in a common set of NAND strings (SetB0). NSB1 has a source end 1903 and a drain end 1901. A slit 1902 is also depicted with other slits. A portion of the bit line BLB0 is also depicted. Dashed lines depict memory cells and select gates, as discussed further below.

Short dashed lines depict memory cells and select gates, as discussed further below. Thus, FIG. 19 shows strings (e.g., NAND strings) of non-volatile storage elements formed above the substrate 1701 in multiple physical levels of a three-dimensional memory array. Each of the strings has an active area comprising a channel that extends vertically through the physical levels. Each string comprises non-volatile storage elements and a drain side select gate in the SGD layer and a source side select gate in the SGS layer. In one embodiment, the source side select gate in the SGS layer is implemented with a vertical TFT 504 having a tunnel barrier.

A region 2069 of the stack is shown in greater detail in FIG. 20A. FIG. 20A depicts a close-up view of the region 2069 of the column C0 of FIG. 19, showing a drain-side select gate SGD0 and a memory cell MC6,0. FIG. 20B depicts a cross-sectional view of the column C0 of FIG. 20A. Each layer is ring-shaped in one possible approach, except the core filler which is cylindrical.

The region 2069 shows portions of the dielectric layers D6 to D8 and the conductive layers WL6 and SG. Each column includes a number of layers which are deposited along the sidewalls of the column. These layers can include oxide-nitride-oxide and polysilicon layers which are deposited, e.g., using atomic layer deposition. For example, a block oxide can be deposited as layer 2096, a nitride such as SiN as a charge trapping layer can be deposited as layer 209, a tunnel oxide can be deposited as layer 2098, a polysilicon body or channel can be deposited as layer 2099, and a core filler dielectric can be deposited as region 2095. The polysilicon body or channel 2099 may also be referred to as an active area. Additional memory cells are similarly formed throughout the columns.

When such a memory cell is programmed, electrons are stored in a portion of the charge trapping layer which is associated with the memory cell. For example, electrons are represented by “-” symbols in the charge trapping layer 2097 for MC6,0. These electrons are drawn into the charge trapping layer from the polysilicon body, and through the tunnel oxide. The threshold voltage of a memory cell is increased in proportion to the amount of stored charge.

A region 2089 of the stack is shown in greater detail in FIG. 21. FIG. 21 depicts a close-up view of the region 2089 of the column C0 of FIG. 19, showing a source-side select gate SGS0 and a memory cell MC0,0. The cross section of the memory cell portion may be similar to that depicted in FIG. 20B.

The region 2089 shows portions of the dielectric layers DO to D2 and the conductive layers SGS and WL0 (as well as the source lint SLB0). For at least the memory cell portion, each column includes a number of layers which are deposited along the sidewalls of the column. These layers can include oxide-nitride-oxide and polysilicon layers which are deposited, e.g., using atomic layer deposition. For example, a block oxide can be deposited as layer 2096, a nitride such as SiN as a charge trapping layer can be deposited as layer 209, a tunnel oxide can be deposited as layer 2098, a polysilicon body or channel can be deposited as layer 2099, and a core filler dielectric can be deposited as region 2095. The polysilicon body or channel 2099 may also be referred to as an active area. Additional memory cells are similarly formed throughout the columns.

The source side select gate SGS0 is implemented with a vertical TFT 504 having a tunnel barrier 509 in this embodiment. The vertical TFT 504 has first source/drain region 501 a, second source/drain region 501 b, channel region 502, tunnel barrier 509, gate(s) 507, and gate dielectric(s) 505. The tunnel barrier 509 may increase the breakdown voltage of the transistor. The tunnel barrier 509 may lower the leakage current (e.g., I_(OFF)) of the transistor. The tunnel barrier 509 is formed from an insulator, in one embodiment. The tunnel barrier 509 is formed from a dielectric material, in one embodiment. Example material for the tunnel barrier 509 include silicon oxide and hafnium oxide. The tunnel barrier 509 could alternatively be located between the channel 502 and the upper source/drain region 501 b.

The first (or lower) source/drain 501 a is in electrical contact with the source line SLB0. Thus, the source line is one example of a lower conductor (see FIG. 1, 514). Note that there could be a thin layer of material, such as titanium nitride, between the lower source/drain 501 a and the source line with the two still being in electrical contact. The second (or upper) source/drain 501 b is in electrical contact with the channel of the vertical NAND string. Specifically, the upper source/drain 501 b is in electrical contact with polysilicon region 2099. Note that there could be a thin layer of material, such as titanium nitride, between the upper source/drain 501 b and the polysilicon region 2099 with the two still being in electrical contact. Region 2099 is not required to be polysilicon. Thus, the NAND string channel is an example of an upper conductor (see, FIG. 1, 516). The vertical thin film transistor (TFT) 504 may be used as a switch to electrically connect/disconnect the source line SLB0 and NAND channel to/from each other. This may allow the vertical TFT 504 with tunnel barrier 509 to be used as a selection device.

The gate(s) 507 are formed from the same material as the word lines, in one embodiment. This might be polysilicon or metal (e.g., tungsten). The gate dielectric 505 may be formed from the same material as regions 2096, 2097, 2098, but that is not required. Recall that regions 2096, 2097, 2098 could be ONO. Thus, one option is to form the gate dielectric 505 during the same process that forms that regions 2096, 2097, 2098. However, the gate dielectric 505 is not required to be formed from the same materials as regions 2096, 2097, 2098.

The source/drain region 501 a, the second source/drain region 501 b, and the channel region 502 are formed from a semiconductor, in one embodiment. As one example, they are formed from silicon, such a polysilicon. The source/drain region 501 a, the second source/drain region 501 b, and the channel region 502 could be formed from the same material as region 2099. In one embodiment, the vertical TFT 514 has a core such as region 2095. Recall that region 2095 may be a silicon oxide core. This may facilitate device fabrication; however, a core is not required.

The first source/drain region 501 a and the second source/drain region 501 b have the same type of conductivity, in one embodiment. For example, they may each be P+ or may each be N+. The channel region 502 has a different type of conductivity than the source/drains 501, in one embodiment. In one embodiment, the regions 501 a, 502, 501 b are N+/P−/N+, respectively. In one embodiment, the regions 501 a, 502, 501 b are P+/N−/P+, respectively. The channel region 502 may be lightly doped or it may be intrinsic. The channel region 502 could also be referred to as a body. The channel region 502 acts as the channel of the TFT 504 during operation.

One embodiment includes a semiconductor device comprising a lower conductor, an upper conductor above the lower conductor, and a vertical thin film transistor (TFT) between the lower conductor and the upper conductor. The vertical TFT comprises a first source/drain region having a first conductivity, a second source/drain region having the first conductivity, a channel region between the first source/drain region and the second source/drain region, and a tunnel barrier that comprises an insulator between either first source/drain region and the channel region or the second source/drain region and the channel region. The first source/drain region is in electrical contact with the lower conductor. The second source/drain region is in electrical contact with the upper conductor. The channel region having a second conductivity. The tunnel barrier comprises silicon oxide in one embodiment. The tunnel barrier comprises hafnium oxide in one embodiment.

The device of the previous paragraph further comprises a three-dimensional memory array having non-volatile storage elements, in one embodiment. The upper conductor is coupled to a group of the non-volatile storage elements in the three-dimensional memory array. The upper conductor is a vertical bit line and the lower conductor is a global bit line in the three-dimensional memory array, in one embodiment. The upper conductor is a channel of a vertical NAND string and the lower conductor is a common source line in the three-dimensional memory array, in one embodiment.

One embodiment includes a method for forming a semiconductor device comprising the following. A lower conductor is formed. A vertically oriented thin film transistor (TFT) is formed comprising the following. A first semiconductor region having a first conductivity is formed over and in electrical contact with the lower conductor. A tunnel barrier is formed over the first semiconductor region. The tunnel barrier comprises an insulator. A second semiconductor region having a second conductivity is formed over the tunnel barrier. A third semiconductor region having the first conductivity is formed over the second semiconductor region. A gate is formed adjacent to the second semiconductor region. An upper conductor is formed over and in electrical contact with the third semiconductor region.

In one embodiment, forming the semiconductor device of the previous paragraph comprises forming a three-dimensional memory array having non-volatile storage elements. Moreover, forming the upper conductor comprises forming a vertically oriented conductive region coupled to a group of the non-volatile storage elements. In one embodiment, forming the lower conductor comprises forming a global bit line and forming the upper conductor comprises forming a vertical bit line in the three-dimensional memory array. In one embodiment, forming the lower conductor comprises forming a common source line and forming the upper conductor comprises forming a channel of a NAND string in the three-dimensional memory array.

One embodiment includes a non-volatile storage system, comprising a substrate, a three dimensional memory array of memory cells positioned above the substrate, a plurality of word lines coupled to the memory cells, a plurality of global bit lines, a plurality of vertically oriented bit lines coupled to the memory cells, and a plurality of vertically oriented thin film transistor (TFT) select devices. The vertically oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines. Each of the vertically oriented TFT select devices comprises: a first semiconductor region having a first conductivity, wherein the first semiconductor region is in electrical contact with a first of the global bit lines; a second semiconductor region having a second conductivity; a third semiconductor region having the first conductivity, wherein the third semiconductor region is in electrical contact with a first of the vertical bit lines, wherein the second semiconductor region is between the first semiconductor region and the second semiconductor region; a tunnel barrier between either the first semiconductor region and the second semiconductor region or between the third semiconductor region and the second semiconductor region, wherein the tunnel barrier comprises an insulator; and a gate adjacent to the second semiconductor region.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the disclosed technology and its practical application, to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. 

What is claimed is:
 1. A semiconductor device comprising: a lower conductor; an upper conductor above the lower conductor; and a vertical thin film transistor (TFT) between the lower conductor and the upper conductor, the vertical TFT comprising: a first source/drain region having a first conductivity, wherein the first source/drain region is in electrical contact with the lower conductor; a second source/drain region having the first conductivity, wherein the second source/drain region is in electrical contact with the upper conductor; a channel region between the first source/drain region and the second source/drain region, the channel region having a second conductivity; and a tunnel barrier that comprises an insulator between either first source/drain region and the channel region or the second source/drain region and the channel region.
 2. The semiconductor device of claim 1, further comprising a three-dimensional memory array having non-volatile storage elements, the upper conductor is coupled to a group of the non-volatile storage elements.
 3. The semiconductor device of claim 2, wherein the lower conductor is a global bit line and the upper conductor is a vertical bit line.
 4. The semiconductor device of claim 2, wherein the three-dimensional memory array comprises a word line, and wherein the vertical TFT further comprises a gate adjacent to the channel region, wherein the gate is in electrical contact with the word line.
 5. The semiconductor device of claim 2, wherein the three-dimensional memory comprises vertical NAND strings that comprise the non-volatile storage elements, wherein the lower conductor is a common source line and the upper conductor is channel of a first of the NAND strings.
 6. The semiconductor device of claim 1, wherein the insulator comprises silicon oxide.
 7. The semiconductor device of claim 1, wherein the first source/drain region is heavily doped, the second source/drain region is heavily doped, and the channel region is lightly doped or intrinsic.
 8. A method for forming a semiconductor device, the method comprising: forming a lower conductor; forming a vertically oriented thin film transistor (TFT), comprising: forming a first semiconductor region having a first conductivity over and in electrical contact with the lower conductor; forming a tunnel barrier over the first semiconductor region, wherein the tunnel barrier comprises an insulator; forming a second semiconductor region having a second conductivity over the tunnel barrier; forming a third semiconductor region having the first conductivity over the second semiconductor region; and forming a gate adjacent to the second semiconductor region; and forming an upper conductor over and in electrical contact with the third semiconductor region.
 9. The method of claim 8, wherein: forming the first semiconductor region comprises forming a first region of silicon that is heavily doped; forming the second semiconductor region comprises forming a second region of silicon that is lightly doped or intrinsic; and forming the third semiconductor region comprises forming a third region of silicon that is heavily doped.
 10. The method of claim 8, further comprising forming a three-dimensional memory array having non-volatile storage elements, wherein forming the upper conductor comprises forming a vertically oriented conductive region coupled to a group of the non-volatile storage elements.
 11. The method of claim 10, wherein forming the lower conductor comprises forming a global bit line and wherein forming the upper conductor comprises forming a vertical bit line.
 12. The method of claim 10, wherein forming the three-dimensional memory comprises forming vertical NAND strings that comprise the non-volatile storage elements, wherein forming the lower conductor comprises forming a common source line and forming the upper conductor comprises forming a channel of a first of the NAND strings.
 13. The method of claim 10, further comprising forming a plurality of word lines in the memory array, wherein forming the gate comprises forming the gate in electrical contact with a first of the word lines.
 14. The method of claim 8, wherein forming the tunnel barrier comprises forming the insulator from silicon oxide.
 15. The method of claim 8, wherein forming the tunnel barrier comprises forming the insulator from hafnium oxide.
 16. A non-volatile storage system, comprising: a substrate; a three dimensional memory array of memory cells positioned above the substrate; a plurality of word lines coupled to the memory cells; a plurality of global bit lines; a plurality of vertically oriented bit lines coupled to the memory cells; and a plurality of vertically oriented thin film transistor (TFT) select devices, the vertically oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines; each of the vertically oriented TFT select devices comprising: a first semiconductor region having a first conductivity, wherein the first semiconductor region is in electrical contact with a first of the global bit lines; a second semiconductor region having a second conductivity; a third semiconductor region having the first conductivity, wherein the third semiconductor region is in electrical contact with a first of the vertical bit lines, wherein the second semiconductor region is between the first semiconductor region and the second semiconductor region; a tunnel barrier between either the first semiconductor region and the second semiconductor region or between the third semiconductor region and the second semiconductor region, wherein the tunnel barrier comprises an insulator; and a gate adjacent to the second semiconductor region.
 17. The non-volatile storage system of claim 16, wherein the first semiconductor region is heavily doped, the second semiconductor region is lightly doped or intrinsic, and the third semiconductor region is heavily doped.
 18. The non-volatile storage system of claim 16, wherein the tunnel barrier is between the first semiconductor region and the second semiconductor region.
 19. The non-volatile storage system of claim 16, wherein the tunnel barrier is between the third semiconductor region and the second semiconductor region.
 20. The non-volatile storage system of claim 16, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region each comprise silicon, the tunnel barrier comprises silicon oxide. 